MITSUBISHI LSIs

M5M5Y5672TG – 25,22,20

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

6

MITSUBISHI

ELECTRIC

Advanced Information

M5M5Y5672TG REV.0.1

Write Operation

Double Late Write

Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3)

are active and the write enable input signal (W#) is asserted low.

Double Late Write means that Data In is required on the third rising edge of clock. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

CLK

A

C

D

E

F

ADD

E1#

ADV

W#

BWx#

DQ

CQ

Q(A)

Q(C)

B

D(B)

D(D)

Read A

Write B

Read C

Write D

Read E

Read F