©2004 Fairchild Semiconductor Corporation

RMWP26001 Rev. C

L

MMIC CHIP

100pF

100pF

L

L

L

100pF

100pF

10,000pF

L

L

L

L

L

100pF

10

µF

L

DRAIN SUPPLY

Vd = +4V

L = BOND WIRE INDUCTANCE

GROUND

(Back of Chip)

GATE SUPPLY

Vg

RF IN

RF OUT

Figure 3. Recommended Application Schematic Circuit Diagram

Figure 4. Recommended Assembly Diagram

Note:

Use 0.003" by 0.0005" Gold Ribbon for bonding. RF input and output bonds should be less than 0.015" long with stress relief.

RF INPUT

RF OUTPUT

L < 0.015"

(4 Places)

Vg (NEGATIVE)

Vdd (POSITIVE)

DIE-ATTACH

80Au/20Sn

2 MIL GAP

5 MIL THICK

ALUMINA

50

Ω

5 MIL THICK

ALUMINA

50

Ω

10

µF

100pF

100pF

100pF

100pF

100pF

10, 000pF