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USB1T1104MHX Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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USB1T1104MHX Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 13 page 3 www.fairchildsemi.com Functional Description The USB1T1104 transceiver is designed to convert CMOS data into USB differential bus signal levels and to convert USB differ- ential bus signal to CMOS data. To minimize EMI and noise the outputs are edge rate controlled with the rise and fall times controlled and defined for full speed data rates. The rise, fall times are balanced between the differ- ential pins to minimize skew. Table 1 describes the specific pin functionality selection. Table 2, Table 3, and Table 4 describe the specific Truth Tables for Driver and Receiver operating functions. The USB1T1104 also has the capability of various power supply configurations to support mixed voltage supply applications (see Table 5) and Power Supply Configurations and Options for detailed descriptions. Functional Tables TABLE 1. Function Select Note 1: Signal levels is function of connection and/or pull-up/pull-down resistors. Note 2: For SUSPND = HIGH mode the differential receiver is inactive and the output RCV output is forced LOW. The out-of-suspend signaling (K) is detected via the single- ended receiver outputs of the Vp and Vm pins. TABLE 2. Driver Function (OE = L) using Differential Input Interface Mode Pin = H Note 3: SE0 = Single Ended Zero TABLE 3. Driver Function (OE = L) using Single-ended Input Interface Mode Pin = L Note 4: SE0 = Single Ended Zero Terminal Number Terminal Name I/O Terminal Description Exposed Diepad GND GND GND supply down bonded to exposed diepad to be connected to the PCB GND. SUSPND OE D , D RCV Vp/Vm Function L L Driving & Receiving Active Active Normal Driving (Differential Receiver Active) L H Receiving (Note 1) Active Active Receiving H L Driving Inactive (Note 2) Active Driving during Suspend (Differential Receiver Inactive) HH 3-STATE (Note 1) Inactive (Note 2) Active Low Power State Vmo Vpo Data L L SE0 (Note 3) L H Differential Logic 1 H L Differential Logic 0 H H Illegal State FSE0 Vo Data L L Differential Logic 0 L H Differential Logic 1 H L SE0 (Note 4) H H SE0 (Note 4) |
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