TECHNICAL DATA

147

Strobed Hex Inverter/Buffer

High-Voltage Silicon-Gate CMOS

The IW4502B consists of six inverter/buffers with 3-state outputs.

A logic “1” on the OUTPUT ENABLE input produces a high

impedance state in all six outputs. This feature permits common busing

of the outputs, thus simplifying system design. A logic “1” on the

DIRECTION input switches all six outputs to logic “0” if the

OUTPUT ENABLE input is a logic “0”.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25

°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

IW4502B

ORDERING INFORMATION

IW4502BN Plastic

IW4502BD SOIC

LOGIC DIAGRAM

PIN 8= GND

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Output

Output

Enable

Direction

A

Y

LL

L

H

LL

H

L

LH

X

L

HX

X

Z

Z = high impedance

X = don’t care