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GM71C4400CLT Datasheet(PDF) 4 Page - LG Semicon Co.,Ltd. |
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GM71C4400CLT Datasheet(HTML) 4 Page - LG Semicon Co.,Ltd. |
4 / 9 page LG Semicon GM71C(S)4400C/CL 4 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter Note Max Unit Min Max Min Max Min tRC Random Read or Write Cycle Time 110 - 130 - 150 - ns tRP RAS Precharge Time 40 - 50 - 60 - ns tRAS RAS Pulse Width 60 10,000 70 10,000 80 10,000 ns tCAS CAS Pulse Width 15 10,000 10,000 10,000 ns 20 20 tASR Row Address Set-up Time 0 - - - ns 0 0 tRAH Row Address Hold Time 10 - - - ns 10 10 tASC Column Address Set-up Time 0 - - - ns 0 0 tCAH Column Address Hold Time 15 - - - ns 15 15 tRCD RAS to CAS Delay Time 20 45 50 60 ns 20 20 8 tRAD RAS to Column Address Delay Time 15 30 35 40 ns 15 15 9 tRSH RAS Hold Time 15 - - - ns 20 20 tCSH CAS Hold Time 60 - - - ns 70 80 tCRP CAS to RAS Precharge Time 10 - - - ns 10 10 tT Transition Time (Rise and Fall) 3 50 50 50 ns 3 3 7 tREF Refresh Period - 16 16 16 ms - - Capacitance (VCC = 5V+/-10%, TA = 25C) Symbol Parameter Note CI1 CI2 CI/O Input Capacitance (Address) Input Capacitance (Clocks) Data Input, Output Capacitance (Data-In, Out) 1 1 1, 2 Unit §Ü §Ü §Ü Max 5 7 10 Min - - - Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT. AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 16) - 128 128 128 ms - - Refresh Period (L-version) tODD OE to DIN Delay Time 15 - - - ns 20 20 tDZO OE Delay Time from DIN 0 - - - ns 0 0 tDZC CAS Set-up Time from DIN 0 - - - ns 0 0 GM71C(S)4400 C/CL-60 GM71C(S)4400 C/CL-70 GM71C(S)4400 C/CL-80 Test Conditions Input rise and fall times: 5ns Input, output timing reference levels: 0.8V, 2.4V Output load : 2 TTL gate + CL (100§Ü) (Including scope and jig) |
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