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LM5071 Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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LM5071 Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 18 page  Detailed Operating Description The LM5071 power interface port and pulse width modula- tion (PWM) controller provides a complete integrated solu- tion for Powered Devices (PD) that connect into Power over Ethernet (PoE) systems. Major features of the PD interface portion of the IC include detection, classification, thermal limit, programmable undervoltage lockout, and current limit monitoring. The device also includes a high-voltage start-up bias regulator that operates over a wide input range up to 60V. The switch mode power supply (SMPS) control portion of the IC includes power good sensing, V CC regulator under- voltage lockout, cycle-by-cycle current limit, error amplifier, slope compensation, softstart, and oscillator sync capability. This high speed BiCMOS IC has total propagation delays less than 100ns and a 1MHz capable oscillator programmed by a single external resistor. The LM5071 PWM controller provides current-mode control for dc-dc converter topologies requiring a single drive output, such as Flyback and Forward topologies. The LM5071 PWM enables all of the advantages of current-mode control including line feed-forward, cycle-by- cycle current limit and simplified loop compensation. The oscillator ramp is internally buffered and added to the PWM comparator input ramp to provide slope compensation nec- essary for current mode control at duty cycles greater than 50% (-80 suffix only). Modes of Operation The LM5071 PD interface is designed to provide a fully compliant IEEE 802.3af system. As such, the modes of operation take into account the barrel rectifiers often utilized to correctly polarize the dc input from the Ethernet cable. Table 1 shows the LM5071 operating modes and associated input voltage range. TABLE 1. Operating Modes With Respect to Input Voltage Input Voltage V IN wrt VEE Mode of Operation 1.8V to 10.0V Detection (Signature) 12.5V to 25.0V Classification 25.0V to UVLO Rising Vth Awaiting Full Power 60V to UVLO Falling Vth Normal Powered Operation An external signature resistor is connected to V EE when VIN exceeds 1.8V, initiating detection mode. During detection mode, quiescent current drawn by the LM5071 is less than 10uA. Between 10.0V and 12.5V, the device enters classifi- cation mode and the signature resistor is disabled. The nominal range for classification mode is 11.5V to 25.0V. The classification current is turned off once the classification range voltage is exceeded, to reduce power dissipation. Between 25.0V and UVLO release, the device is in a standby state, awaiting the input voltage to reach the opera- tional range to complete the power up sequence. Once the V IN voltage increases above the upper UVLO threshold volt- age, the internal power MOSFET is enabled to deliver a constant current to charge the input capacitor of the dc-dc converter. When the MOSFET Vds voltage falls below 1.5V, the internal Power Good signal enables the SMPS controller. The LM5071 is specified to operate with an input voltage as high as 60.0V. The SMPS controller and internal MOSFET are disabled when V IN falls to the lower UVLO threshold. Detection Signature To detect a potential powered device candidate, the PSE (Power Sourcing Equipment) will apply a voltage from 2.8V to 10V across the input terminals of the PD. The voltage can be of either polarity so a diode barrel network is required on both lines to ensure this capability. The PSE will take two measurements, separated by at least 1V and 2ms of time. The voltage ramp between measurement points will not exceed 0.1V/us. The delta voltage / delta current calculation is then performed; if the detected impedance is above 23.75k Ω and below 26.25kΩ, the PSE will consider a PD to be present. If the impedance is less than 15k Ω or greater than 33k Ω a PD will be considered not present and will not receive power. Impedances between these values may or may not indicate the presence of a valid PD. The LM5071 will enable the signature resistor at a controller input voltage of 1.5V to take into account the diode voltage drops. An external signature resistor should be placed between the VIN and RSIG pins. The signature resistor is in parallel with the external UVLO resistor divider, and its value should be calculated accordingly. Targeting 24.5k Ω increases margin in the signature design as the input bridge rectifier diodes contribute to the series resistance measured at the PD input terminals. The PSE will tolerate no more than 1.9V of offset voltage (caused by the external diodes) or more than 10uA of offset current (bias current). The input capacitance must be greater than 0.05uF and less than 0.12uF. To increase efficiency, the signature resistor is disabled by the LM5071 controller once the input voltage is above the detection range (> 11V). Classification To classify the PD, the PSE will present a voltage between 14.5V and 20.5V to the PD. The LM5071 enables classifica- tion mode at a nominal input voltage of 11.5V. An internal 1.5V linear regulator and an external resistor connected to the RCLASS pin provide classification programming current. Table 2 shows the external classification resistor required for a particular class. The classification current flows through the IC into the clas- sification resistor. The suggested resistor values take into account the bias current flowing into the IC. A different desired RCLASS can be calculated by dividing 1.5V by the desired classification current. Per the IEEE 802.3af specification, classification is optional, and the PSE will default to class 0 if a valid classification current is not detected. If PD classification is not desired (i.e., Class 0), simply leave the RCLASS pin open. The classification time period may not last longer than 75ms as per IEEE 802.3af. The LM5071 will remain in classification mode until V IN is greater than 25V. www.national.com 10 |
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