2 / 19 page  XT April 1999 4.5.99 2 )6)6)6)6 /RZ6NHZ &ORFN)DQRXW%XIIHU ,&V ,62 Table 1: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI U = Input with Internal Pull-Up; DI D = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN (FS6050) PIN (FS6051) PIN (FS6053) PIN (FS6054) TYPE NAME DESCRIPTION 11 9 9 9 DI CLK_IN Clock input for SDRAM clock outputs 25 15 15 15 DI U SCL Serial clock input 24 14 14 14 DI UO SDA Serial data input/output 4222 DO SDRAM_0 5333 DO SDRAM_1 8666 DO SDRAM_2 9777 DO SDRAM_3 13 - - - DO SDRAM_4 14 - - - DO SDRAM_5 17 - 10 10 DO SDRAM_6 18 - 11 11 DO SDRAM_7 SDRAM clock outputs (Byte 0) 31 - 18 18 DO SDRAM_8 32 - 19 19 DO SDRAM_9 35 - - - DO SDRAM_10 36 - - - DO SDRAM_11 40 22 22 22 DO SDRAM_12 41 23 23 23 DO SDRAM_13 44 26 26 26 DO SDRAM_14 45 27 27 27 DO SDRAM_15 SDRAM clock outputs (Byte 1) 21 11 12 12 DO SDRAM_16 28 18 - 17 DO SDRAM_17 SDRAM feedback clock outputs (Byte 2) 38 20 - 20 DI U OE Output enable tristates all clock outputs when low 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 1, 5, 10, 19, 24, 28 1, 5, 20, 24, 28 1, 5, 24, 28 P VDD 3.3V ± 5% power supply for SDRAM clock buffers 23 13 13 13 P VDD_I 2C 3.3V ± 5% power supply for serial communications 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 4, 8, 12, 17, 21, 25 4, 8, 17, 21, 25 4, 8, 21, 25 P VSS Ground for SDRAM clock buffers 26 16 16 16 P VSS_I 2C Ground for serial communications 1, 2, 47, 48 - - - - (reserved) Reserved Figure 4: Pin Configuration (FS6053) FS6053 Figure 5: Pin Configuration (FS6054) FS6054 |
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