138

80C286/883

NOTES:

1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.

4. For HOLD request set up to HLDA, refer to Figure 8.

6. The data bus will remain in a high impedance state if a read cycle is performed.

FIGURE 5. EXITING AND ENTERING HOLD

16

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

BUS CYCLE TYPE

CLK

HILDA

16

(SEE NOTE 4)

12A (NOTE 3)

15

(SEE NOTE 3)

12B

15

S1 • S0

PEACK

BHE, LOCK

M/IO,

COD/INTA

(SEE NOTE 5)

13

(SEE NOTE 1)

15

VALID

14

(SEE NOTE 6)

(SEE NOTE 2)

15

VALID IF WRITE

PCLK

IF NPX TRANSFER