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HFA3101B Datasheet(PDF) 1 Page - Intersil Corporation |
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HFA3101B Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 12 page 1 ® FN3663.5 HFA3101 Gilbert Cell UHF Transistor Array The HFA3101 is an all NPN transistor array configured as a Multiplier Cell. Based on Intersil’s bonded wafer UHF-1 SOI process, this array achieves very high fT (10GHz) while maintaining excellent hFE and VBE matching characteristics that have been maximized through careful attention to circuit design and layout, making this product ideal for communication circuits. For use in mixer applications, the cell provides high gain and good cancellation of 2nd order distortion terms. Pinout HFA3101 (SOIC) TOP VIEW Features • Pb-free Available as an Option • High Gain Bandwidth Product (fT) . . . . . . . . . . . . . 10GHz • High Power Gain Bandwidth Product . . . . . . . . . . . . 5GHz • Current Gain (hFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 • Low Noise Figure (Transistor) . . . . . . . . . . . . . . . . . 3.5dB • Excellent hFE and VBE Matching • Low Collector Leakage Current . . . . . . . . . . . . . . <0.01nA • Pin to Pin Compatible to UPA101 Applications • Balanced Mixers • Multipliers • Demodulators/Modulators • Automatic Gain Control Circuits • Phase Detectors • Fiber Optic Signal Processing • Wireless Communication Systems • Wide Band Amplification Stages • Radio and Satellite Communications • High Performance Instrumentation Ordering Information PART NUMBER (BRAND) TEMP. RANGE (°C) PACKAGE PKG. DWG. # HFA3101B (H3101B) -40 to 85 8 Ld SOIC M8.15 HFA3101BZ (H3101B) (Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 HFA3101B96 (H3101B) -40 to 85 8 Ld SOIC Tape and Reel M8.15 HFA3101BZ96 (H3101B) (Note) -40 to 85 8 Ld SOIC Tape and Reel (Pb-free) M8.15 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. Q5 Q6 Q1 Q2 Q3 Q4 NOTE: Q5 and Q6 - 2 Paralleled 3µm x 50µm Transistors Q1, Q2, Q3, Q4 - Single 3µm x 50µm Transistors Data Sheet September 2004 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 1998, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. |
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