HI1-7151S-2 datasheet(6/17 Pages) INTERSIL

Part #	HI1-7151S-2

Description	10-Bit, High Speed, A/D Converter with Track and Hold

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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AC Electrical Specifications V+ = 5V ±10%, V- = -5V ±10%, VREF = 2.5V, TA = 25oC, fCLK = 300kHz, 50% Duty Cycle,

CL = 100pF (including stray for D0 - D9, OVR, HOLD, BUSY), Unless Otherwise Specified (Note 11)

PARAMETER

SYMBOL

NOTES

25oC0oC to 75oC-40oC to 85oC

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Clock Input Duty Cycle

D

5

4550

55455545

55

%

Continuous Conversion Time

tSPS

9

-

3tck

-

3tck

-

3tck

µs

9

60

-

10

60

10

60

10

µs

Slow Memory Mode Conversion

Time

tCONV

5, 8

-

4tck

+0.9

-4tck

+0.9

-4tck

+0.9

µs

Continuous Throughput

tCYC

9-

-

fCLK/3

-

fCLK/3

-

fCLK/3/

3

sps

CLOCK Period

tCK

--

1/fCLK

--

-

CLOCK to HOLD Rise Delay

tCKHR

5

150

290

500

140

525

120

525

ns

WR Pulse Width

tWRL

5, 8, 10

200

113

tck/2

225

tck/2

225

tck/2

ns

WR to HOLD Delay

tHOLD

5, 8

-

80

170

-

200

-

200

ns

Busy to Data

tBD

5, 8

-

40

200

-

230

-

230

ns

WR to RD Active

tWRD

5, 8

100

-

100

-

100

-

ns

CLOCK to HOLD Fall Delay

tCKHF

5, 950125

25040275

25

275

ns

HOLD to DATA change

tDATA

5, 9

100

200

400

90

550

70

550

ns

RD LO to Active

tRD

5, 13

-

75

150

-

190

-

190

ns

RD HI to Inactive

tRX

5, 14

-

25

60

-

80

-

80

ns

HBE to DATA

tAD

5

-

70

150

-

165

-

165

ns

CS to DATA

tCD

5

-

95

180

-

210

-

210

ns

RD to BUSY

tBUSY

5

-

35

200

-

200

-

200

ns

Rise Time

tr

5, 12

-

50

100

-

125

-

125

ns

Fall Time

tf

5, 12

-

45

100

-

120

-

120

ns

NOTES:

8. Slow memory mode timing.

9. Fast memory or DMA mode of operation, except the first conversion which is equal to tCONV.

10. Maximum specification to prevent multiple triggering with WR.

11. All input drive signals are specified with tr = tf ≤ 20ns and shall swing from VIL -0.4V to VIH +0.4V for all timing specifications. A signal is

considered to change state as it crosses a 1.4V threshold (except tRD and tRX).

12. tr and tf load is CL = 100pF (including stray capacitance) to DG and is measured from the 10 - 90% point.

13. tRD is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. High-Z to VOH is

measured with RL = 2.5kΩ and CL = 100pF (including stray) to DG. High-Z to VOL is measured with RL = 2.5kΩ to V+ and CL = 100pF

(including stray) to DG.

14. trx is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. VOH to High-Z is

measured with RL = 2.5kΩ and CL = 10pF (including stray) to DG. VOL to High-Z is measured with RL = 2.5 kΩ to V+ and CL = 10pF

(including stray) to DG.

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HI1-7151S-2 Datasheet(PDF) 6 Page - Intersil Corporation

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