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5962R9666301TEC Datasheet(PDF) 3 Page - Intersil Corporation |
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5962R9666301TEC Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 3 page 3 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Die Characteristics DIE DIMENSIONS: 2450 µm x 4950µm x 533µm ±25.4µm (97 x 195 x 21mils ±1mil) METALLIZATION: M1: Mo/Tiw Thickness: 5800 Å M2: Al/Si/Cu Thickness: 10k Å ±1kÅ SUBSTRATE POTENTIAL: Internally connected to VDD. May be left floating. BACKSIDE FINISH: Silicon PASSIVATION: Type: SiO2 Thickness: 8k Å ±1kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 285 PROCESS: Radiation Hardened CMOS, AVLSI Metallization Mask Layout HS-26C31RH (14) DO (13) DO (12) ENABLE (11) CO (10) CO AO (2) AO (3) ENABLE (4) BO (5) BO (6) HS-26C31RH-T |
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