11-11

HS-83C55RH

Functional Description

ROM Section

The HS-83C55RH contains an 8-bit address latch which

allows it to interface directly to the HS-80C85RH Micropro-

cessor without additional hardware.

The R0M section of the Chip is addressed by an 11-bit

address and the Chip Enables. The address and levels on

the Chip Enable pins are latched into the address latches on

the falling edge of ALE. If the latched Chip Enables are

active and IO/M is low when RD goes low, the contents of

the R0M location addressed by the latched address are put

out through AD0-7 output buffers.

I/O Section

The I/O section of the chip is addressed by the latched value

of AD0-1. Two 8-bit Data Direction Registers (DDR) in the

HS-83C55RH determine the input/output status of each pin

in the corresponding ports. A “O” in a particular bit position of

a DDR signifies that the corresponding I/O port bit is in the

input mode. A “1” in a particular bit position signifies that the

corresponding I/O port bit is in the output mode. In this

manner the I/O ports of the HS-83C55RH are bit-by-bit

programmable as inputs or outputs. The table summarizes

port and DDR designation. DDR’s Cannot be read.

When IOW goes low and the Chip Enables are active, the

data on the AD0-7 is written into the I/O port selected by the

latched value of AD0-1. During this operation all I/O bits of

selected port are affected, regardless of their I/O mode and

the state of IO/M. The actual output level does not change

until IOW returns high (glitch free output). A port can be read

out when the latched Chip Enables are active and either RD

goes low with IO/M high, or IOR goes low. Both input and

output mode bits of a selected port will appear on lines

AD0-7.

To clarify the function of the I/O ports and Data Direction

Registers, Figure 1 shows the configuration of one bit of

PORT A and DDR A. The same logic applies to PORT B and

DDR B.

Note that hardware RESET or writing a zero to the DDR

latch will cause the output latch’s output buffer to be dis-

abled, preventing the data in the output latch from being

passed through to the pin. This is equivalent to putting the

port in the input mode. Note also that the data can be written

to the Output Latch even though the Output Buffer has been

disabled. This enables a port to be initialized with a value

prior to enabling the output.

Figure 1 also shows that the contents of PORT A and PORT

B can be read even when the ports are configured as out-

puts.

System Interface with HS-8OC85RH

A system using the HS-83C55RH can use either one of the

two I/O Interface techniques:

• Standard I/O

• Memory Mapped I/O

If a standard I/O technique is used, the system can use the

feature of both CE2 and CE1. By using a combination of

unused address lines A11-15 and the Chip Enable inputs,

the system can use up to 5 each HS-83C55RHs without

requiring a CE decoder. See Figure 3.

If a memory mapped I/O approach is used the HS-83C55RH

will be selected by the combination of both the Chip Enables

and IO/M using AD8-15 address lines. See Figure 2.

FIGURE 1. HS-83C55RH ONE BIT OF PORT A AND DDR A

FIGURE 2. HS-83C55RH IN HS-80C85RH SYSTEM (MEMO-

RY\MAPPED I/O)

AD1

AD0

Selection

0

0

Port A

01

Port B

1

0

Port A Data Direction Register (DDR A)

1

1

Port B Data Direction Register (DDR B)

Write PA = (IOW = 0) (Chip Enables Active) (Port A Address Selected)

Write DDR A = (IOW = 0) (Chip Enables Active) (DDR A Address Selected)

Read PA = {[(IO/M = 1) (RD = 0)] + (IOR = 0)} (Chip Enables Active)

(Port A Address Selected)

NOTE: Write PA is not qualified by IO/M.

ONE BIT OF PORT A AND DDR A:

HS-83C55RH

D0

OUTPUT

LATCH

CLK

DQ

DDR

LATCH

CLK

DQ

CLR

D0

D0

WRITE PA

RESET

WRITE DDR A

OUTPUT

ENABLE

READ PA

PA0

PIN

HS-83C55RH

A8-15

VDD

HS-83C55RH

ALE

RD

WR

IO/M

READY

CLK (

φ2)

VDD

AD0-7