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AM29DL642G90MDI Datasheet(PDF) 4 Page - Advanced Micro Devices |
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AM29DL642G90MDI Datasheet(HTML) 4 Page - Advanced Micro Devices |
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4 / 54 page  2 Am29DL642G June 10, 2005 PRELIMINARY GENERAL DESCRIPTION The Am29DL642G is a 128 Mbit, 3.0 Volt (2.7 V to 3.6 V) that combines two Am29DL640G single power supply flash memory devices in a single 63-ball Fortified BGA package. Each Am29DL640G is a 64 Mbit, 3.0 Volt (2.7 V to 3.6 V) device organized as 4,194,304 words. Data ap- pears on DQ15-DQ0. The device is designed to be pro- grammed in-system with the standard system 3.0 volt V CC supply. A 12.0 volt VPP is not required for program or erase operations. The Am29DL642G is equipped with two CE# inputs for flexible selection between the two in- ternal 64 Mb devices. The device can also be pro- grammed in standard EPROM programmers. The Am29DL642G offers an access time of 70 or 90 ns. To eliminate bus contention the Am29DL642G device has two separate chip enables (CE# and CE2#). Each chip enable (CE# or CE2#) is connected to only one of the two dice in the Am29DL642G package. To the system, this de vice will be the same as two inde pendent Am29DL640G on the same board. The only difference is that they are now packaged together to reduce board space. Each device requires only a single 3.0 Volt power sup- ply (2.7 V to 3.6 V) for both read and write functions. In- ternally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides si- multaneous operation by dividing the memory space of each Am29DL640G device into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed, system soft- ware can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im- prove overall system performance by allowing a host sys- tem to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. Each Am29DL640G can be organized as both a top and bottom boot sector configuration. Am29DL642G Features The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is perma- nently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Elec- tronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system soft- ware to be simplified, as it will perform all functions nec- essary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is lo- cated in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations dur- ing power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The sys- tem can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Bank Megabits Sector Sizes Bank 1 8 Mb Eight 4 Kword, Fifteen 32 Kword Bank 2 24 Mb Forty-eight 32 Kword Bank 3 24 Mb Forty-eight 32 Kword Bank 4 8 Mb Eight 4 Kword, Fifteen 32 Kword |
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