LPC47S422QFP datasheet(11/264 Pages) SMSC

Part #	LPC47S422QFP

Description	ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS

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Manufacturer	SMSC [SMSC Corporation]

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Note 2: The nLPCPD pin may be tied high.

The LPC interface will function properly if the

nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin Count

Interface Specification”.

Note 3: If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the

configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz

clock is connected. This bit determines the clock source for the fan tachometer, LED and

“wake on specific key” logic. Set this bit to ‘1’ if the clock is not connected.

Note 4: The fan control pin (FAN) comes up as output and low following a VCC POR and Hard Reset.

This pin reverts to its non-inverting General Purpose I/O output function when VCC is removed

from the part.

Note 5: The GP53/TXD2/IRTX pin is an output and low when the part is under VTR power (VCC=0).

The pin comes up as output and low following a VCC POR and Hard Reset.

Note 6: VTR can be connected to VCC if no wakeup functionality is required.

Note 7: The GP24/SYSOPT pin requires an external pulldown resistor to put the base I/O address for

configuration at 0x02E. An external pullup resistor is required to move the base I/O address

for configuration to 0x04E.

Note 8: External pullups must be placed on the nKBDRST and A20M pins. These pins are General

Purpose I/Os that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M

functions are to be used, the system must ensure that these pins are high. See Section “Pins

That Require External Pullup Resistor”.

Note 9: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under

VTR power. The GP61 pin defaults to the LED function active (blinking at a 1Hz rate, 50%

duty cycle) on initial power up (as long as the 32 kHz clock input is active).

Note 10: External pullups are required on the nXRD and nXWR pins.

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