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SST39VF800-70-4I-EK Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST39VF800-70-4I-EK Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
5 / 23 page 5 © 1999 Silicon Storage Technology, Inc. 343-04 2/99 8 Megabit Multi-Purpose Flash SST39VF800Q / SST39VF800 Advance Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# A9 DQ Address Read VIL VIL VIH AIN DOUT AIN Program VIL VIH VIL AIN DIN AIN Erase VIL VIH VIL X X Sector or block address, XXh for chip erase Standby VIH X X X High Z X Write Inhibit X VIL X X High Z/ DOUT X XXVIH X High Z/ DOUT X Product Identification Hardware Mode VIL VIL VIH VH Manufacturer Code (00BF) A18 - A1 = VIL, A0 = VIL Device Code (2781) A18 - A1 = VIL, A0 = VIH Software Mode VIL VIL VIH AIN See Table 4 343 PGM T3.0 TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A18-A0 Address Inputs To provide memory addresses. During sector erase A18-A11 address lines will select the sector. During block erase A18-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the write operations. VDD Power Supply To provide 3-volt supply (2.7-3.6V) VDDQ I/O Power Supply Supplies power for input/output buffers. It should be either tied to VDD (2.7 - 3.6V) for 3V I/O or to a 5.0V (4.5 - 5.5V) power supply to support 5V I/O. (Not offered on SST39VF800 device, instead it is a NC) Vss Ground NC No Connection Unconnected pins. 343 PGM T2.0 |
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