M393T6553CZ3 datasheet(5/21 Pages) SAMSUNG

Part #	M393T6553CZ3

Description	DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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Rev. 1.2 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs

DDR2 SDRAM

Functional Block Diagram: 512MB, 64Mx72 Module(populated as 1 rank of x8 DDR2 SDRAMs)

RS0

DQS0

DM0/DQS9

NC/DQS9

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

DQS1

DM1/DQS10

NC/DQS10

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

DQS2

DM2/DQS11

NC/DQS11

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

DQS3

DM3/DQS12

NC/DQS12

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

DQS8

DM8/DQS17

NC/DQS17

DM/

RDQS

NU/

RDQS

CS DQS DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D8

DQS4

DM4/DQS13

NC/DQS13

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D4

DQS5

DM5/DQS14

NC/DQS14

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D5

DQS6

DM6/DQS15

NC/DQS15

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D6

DQS7

DM7/DQS16

NC/DQS16

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D7

A0

Serial PD

A1 A2

SA0 SA1 SA2

SCL

SDA

VSS

D0 - D8

VDD/VDDQ

D0 - D8

VREF

VDDSPD

Serial PD

WP

Notes :

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. Unless otherwise noted, resister values are 22 Ohms

1:1

R

E

G

I

S

T

E

R

RST

S0*

BA0-BA1

A0-A13

RAS

CAS

WE

CKE0

ODT0

RESET

PCK7

RSO-> CS : DDR2 SDRAMs D0-D8

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8

RRAS -> RAS : DDR2 SDRAMs D0-D8

RCAS -> CAS : DDR2 SDRAMs D0-D8

RWE -> WE : DDR2 SDRAMs D0-D8

RCKE0 -> CKE : DDR2 SDRAMs D0-D8

RODT0 -> ODT0 : DDR2 SDRAMs D0-D8

P

L

OE

CK0

RESET

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8

PCK7 -> CK : Register

* S0 connects to DCS and VDD connects to CSR on the register.

M393T6553CZ3 / M393T6553CZA

Signals for Address and Command Parity Function (M393T6553CZA)

VSS

PAR_IN

C0

C1

PPO

QERR

Err_Out

Register

PAR_IN

100K ohms

The resistors on Par_In, A13, A14, A15, BA2 and the

signal line of Err_Out refer to the section: "Register

Options for Unused Address inputs"

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