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M393T5750CZA-CE6 Datasheet(PDF) 2 Page - Samsung semiconductor |
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M393T5750CZA-CE6 Datasheet(HTML) 2 Page - Samsung semiconductor |
2 / 21 page Rev. 1.2 Aug. 2005 512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM DDR2 Registered DIMM Ordering Information Note: “Z” of Part number(11th digit) stand for Lead-free products. Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products. Note: "A" of Part number(12th digit) stand for Parity Register products. Part Number Density Organization Component Composition Number of Rank Parity Register Height M393T6553CZ3-CD5/CC 512MB 64Mx72 64Mx8(K4T51083QC)*9EA 1 X 30mm M393T6553CZA-CE7/E6/D5/CC 512MB 64Mx72 64Mx8(K4T51083QC)*9EA 1 O 30mm M393T2953CZ3-CD5/CC 1GB 128Mx72 64Mx8(K4T51083QC)*18EA 2 X 30mm M393T2953CZA-CE7/E6/D5/CC 1GB 128Mx72 64Mx8(K4T51083QC)*18EA 2 O 30mm M393T2950CZ3-CD5/CC 1GB 128Mx72 128Mx4(K4T51043QC)*18EA 1 X 30mm M393T2950CZA-CE7/E6/D5/CC 1GB 128Mx72 128Mx4(K4T51043QC)*18EA 1 O 30mm M393T5750CZ3-CD5/CC 2GB 256Mx72 128Mx4(K4T51043QC)*36EA 2 X 30mm M393T5750CZA-CE7/E6/D5/CC 2GB 256Mx72 128Mx4(K4T51043QC)*36EA 2 O 30mm Features • Performance range • JEDEC standard 1.8V ± 0.1V Power Supply •VDDQ = 1.8V ± 0.1V • 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin • 4 Banks • Posted CAS • Programmable CAS Latency: 3, 4, 5 • Programmable Additive Latency: 0, 1 , 2 , 3 and 4 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination with selectable values(50/75/150 ohms or disable) • PASR(Partial Array Self Refresh) • Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. E7(DDR2-800) E6(DDR2-667) D5(DDR2-533) CC(DDR2-400) Unit Speed@CL3 400 400 400 400 Mbps Speed@CL4 533 533 533 400 Mbps Speed@CL5 800 667 - -Mbps CL-tRCD-tRP 5-5-5 5-5-5 4-4-4 3-3-3 CK Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 128Mx4(512Mb) based Module A0-A13 A0-A9,A11 BA0-BA1 A10 64Mx8(512Mb) based Module A0-A13 A0-A9 BA0-BA1 A10 |
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