Specifications ispLSI 2128V

6

Over Recommended Operating Conditions

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Table 2-0036/2128V

Inputs

UNITS

-80

MIN.

-60

MIN.

MAX.

MAX.

DESCRIPTION

#

2

PARAMETER

20 Input Buffer Delay

––

0.6

ns

21 Dedicated Input Delay

––

1.4

ns

22 GRP Delay

––

2.1

ns

GLB

25 1 Product Term/XOR Path Delay

––

12.3

ns

26 20 Product Term/XOR Path Delay

––

12.3

ns

27 XOR Adjacent Path Delay

––

14.4

ns

28 GLB Register Bypass Delay

––

1.3

ns

29 GLB Register Setup Time before Clock

–

0.2

–

ns

30 GLB Register Hold Time after Clock

–

8.0

–

ns

31 GLB Register Clock to Output Delay

––

1.6

ns

3

32 GLB Register Reset to Output Delay

––

2.8

ns

33 GLB Product Term Reset to Register Delay

––

9.3

ns

34 GLB Product Term Output Enable to I/O Cell Delay

––

10.4

ns

35 GLB Product Term Clock Delay

6.5

9.3

ns

ORP

38 Output Buffer Delay

––

2.2

ns

39 Output Slew Limited Delay Adder

––

12.2

ns

0.4

1.3

GRP

1.2

23 4 Product Term Bypass Path Delay (Combinatorial)

––

9.6

ns

24 4 Product Term Bypass Path Delay (Registered)

––

10.3

ns

9.2

9.5

11.3

0.3

5.8

7.5

0.2

5.4

1.6

2.5

5.6

8.5

3.8

5.6

36 ORP Delay

––

1.5

ns

37 ORP Bypass Delay

––

0.5

ns

1.4

0.4

Outputs

2.2

12.2

40 I/O Cell OE to Output Enabled

––

4.9

ns

41 I/O Cell OE to Output Disabled

––

4.9

ns

4.9

4.9

42 Global Output Enable

––

7.1

ns

5.1

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

2.3

4.2

4.2

ns

44 Clock Delay, Y1 or Y2 to Global GLB Clock Line

2.3

4.2

4.2

ns

Clocks

2.3

2.3

45 Global Reset to GLB

––

9.5

ns

Global Reset

7.9