2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

_______________________________________________________________________________________

3

Note 2: Minimum SCL clock frequency is limited by the MAX7311 bus timeout feature, which resets the serial bus interface if either

SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation.

signal) in order to bridge the undefined region SCL’s falling edge.

specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the

Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

DC ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Leakage Current

-1

+1

µA

Input Capacitance

4pF

INT

Low-Level Output Current

6

mA

AC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCL Clock Frequency

(Note 2)

400

kHz

Bus Timeout

29

61

ms

Bus Free Time Between STOP

and START Conditions

Figure 2

1.3

µs

Hold Time (Repeated) START

Condition

Figure 2

0.6

µs

Repeated START Condition

Setup Time

Figure 2

0.6

µs

STOP Condition Setup Time

Figure 2

0.6

µs

Data Hold Time

Figure 2 (Note 3)

0.9

µs

Data Setup Time

Figure 2

100

ns

SCL Low Period

Figure 2

1.3

µs

SCL High Period

Figure 2

0.7

µs

V+ < 3.3V

500

SDA Fall Time

Figure 2 (Notes 4, 5)

V+

≥ 3.3V

250

ns

Pulse Width of Spike Suppressed

(Note 6)

50

ns

PORT TIMING

Output Data Valid

Figure 7

3

µs

Input Data Setup Time

27

µs

Input Data Hold Time

0µs

INTERRUPT TIMING

Interrupt Valid

Figure 9

30.5

µs

Interrupt Reset

Figure 9

2

µs