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MC68HC908GT16CB Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC68HC908GT16CB Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 278 page  Revision History MC68HC908GT16 • MC68HC908GT8 Data Sheet, Rev. 3 4 Freescale Semiconductor June, 2002 2.0 Figure 2-2. Control, Status, and Data Registers — Corrected ESCI arbiter data register (SCIADAT) to reflect read-only status 50 Figure 14-19. ESCI Arbiter Control Register (SCIACTL) — Corrected address location designator from $0018 to $000A 170 Figure 14-20. ESCI Arbiter Data Register (SCIADAT) — Corrected address location designator from $0019 to $000B 171 September, 2004 3.0 Reformatted to meet current publications standards Throughout 1.5.6 ADC Reference Pins (VREFH and VREFL) — Corrected connections 24 2.6.3 FLASH Page Erase Operation — Updated procedure 39 2.6.4 FLASH Mass Erase Operation — Updated procedure 40 2.6.5 FLASH Program/Read Operation — Updated procedure 41 2.6.6 FLASH Block Protection — Description updated for clarity 43 3.3.5 Conversion — Updated for clarity 50 3.6.3 ADC Voltage Reference High Pin (VREFH) — Corrected connections 51 3.6.4 ADC Voltage Reference Low Pin (VREFL) — Corrected connections 51 3.7.1 ADC Status and Control Register — Updated description of the COCO bit 52 Chapter 4 Configuration Register (CONFIG) — Updated COP tmeout selections 55, 57 Chapter 4 Configuration Register (CONFIG) — Updted SSREC bit usage 58 Chapter 5 Computer Operating Properly (COP) Module — Updated timeout selections 60 Figure 5-1. COP Block Diagram — Updated illustration for clarity 59 Table 6-1. Instruction Set Summary — Updated definitions for STOP and WAIT 68 Figure 7-9. Code Example for Switching Clock Sources — Replaced example code 87 Figure 7-10. Code Example for Enabling the Clock Monitor — Replaced example code 88 Figure 14-18. ESCI Prescaler Register (SCPSC) — Corrected address location 170 Chapter 15 System Integration Module (SIM) — Clarified SIM features and functionality 177, 180, 181, 182 15.7.2 SIM Reset Status Register — Clarified SRSR operation 192 Table 19-1. Monitor Mode Signal Requirements and Options — Reworked 245 19.2.1 Functional Description — Corrected Break description 235, 238 19.3 Monitor Module (MON) — Reworked 241 Chapter 20 Electrical Specifications — Revised/added tables: 20.5 5.0-V DC Electrical Characteristics 20.6 3.0-V DC Electrical Characteristics 20.7 Supply Current Characteristics 20.8 5-V Control Timing 20.9 3-V Control Timing 255 256 257 258 258 20.20 Memory Characteristics — Updated memory table 271 Chapter 20 Electrical Specifications — Added figures: Figure 20-1. RST and IRQ Timing Figure 20-2. RST and IRQ Timing 258 258 Revision History (Sheet 2 of 2) Date Revision Level Description Page Number(s) |
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