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XRT83SL34 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT83SL34 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 80 page XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.0.8 II Figure 12. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. 28 TRANSMITTER (CHANNELS 0 - 3) ............................................................................................................ 29 Transmit Termination Mode ...................................................................................................................... 29 External Transmit Termination Mode ........................................................................................................ 29 Figure 13. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 29 TABLE 8: TRANSMIT TERMINATION CONTROL ....................................................................................... 29 TABLE 9: TERMINATION SELECT CONTROL .......................................................................................... 29 REDUNDANCY APPLICATIONS ............................................................................................................. 30 TABLE 10: TRANSMIT TERMINATION CONTROL ..................................................................................... 30 TABLE 11: TRANSMIT TERMINATIONS ................................................................................................... 30 TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 31 Figure 14. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 32 Figure 15. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............. 32 Figure 16. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 33 Figure 17. Simplified Block Diagram - Receive Section for N+1 Redundancy .......................... 34 PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 35 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 35 NETWORK LOOP CODE DETECTION AND TRANSMISSION .............................................................................. 35 TABLE 12: PATTERN TRANSMISSION CONTROL ..................................................................................... 35 TABLE 13: LOOP-CODE DETECTION CONTROL ..................................................................................... 35 TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 36 LOOP-BACK MODES ................................................................................................................................... 37 TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ........................................................................ 37 TABLE 15: LOOP-BACK CONTROL IN HOST MODE ................................................................................. 37 LOCAL ANALOG LOOP-BACK (ALOOP) ....................................................................................................... 38 REMOTE LOOP-BACK (RLOOP) ................................................................................................................. 38 Figure 18. Local Analog Loop-back signal flow ........................................................................... 38 Figure 19. Remote Loop-back mode with jitter attenuator selected in receive path ................. 38 DIGITAL LOOP-BACK (DLOOP) .................................................................................................................. 39 Figure 20. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 39 Figure 21. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 39 DUAL LOOP-BACK ...................................................................................................................................... 40 Figure 22. Signal flow in Dual loop-back mode ............................................................................ 40 MICROPROCESSOR PARALLEL INTERFACE .............................................................. 41 TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ........................................................... 41 MICROPROCESSOR REGISTER TABLES ........................................................................................................ 42 TABLE 17: MICROPROCESSOR REGISTER ADDRESS ............................................................................. 42 TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION ................................................................. 42 MICROPROCESSOR REGISTER DESCRIPTIONS ............................................................................................. 45 TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ........................................................... 45 TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ........................................................... 46 TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ........................................................... 48 TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ........................................................... 50 TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ........................................................... 52 TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ........................................................... 53 TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ........................................................... 55 TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ........................................................... 56 TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ........................................................... 57 TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ........................................................... 57 TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION ......................................................... 58 TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION ......................................................... 58 TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION ......................................................... 59 TABLE 32: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION ......................................................... 59 TABLE 33: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION ......................................................... 60 |
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