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XRT83SL34 Datasheet(PDF) 1 Page - Exar Corporation |
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XRT83SL34 Datasheet(HTML) 1 Page - Exar Corporation |
1 / 80 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com PRELIMINARY XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FEBRUARY 2004 REV. P1.0.8 GENERAL DESCRIPTION The XRT83SL34 is a fully integrated Quad (four channel) short-haul line interface unit for T1 (1.544Mbps) 100 Ω, E1 (2.048Mbps) 75Ω or 120Ω, or J1 110 Ω applications. In T1 applications, the XRT83SL34 can generate five transmit pulse shapes to meet the short-haul Digital Cross-Connect (DSX-1) template requirements. It also provides programmable transmit pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The XRT83SL34 provides both a parallel Host microprocessor interface as well as a Hardware mode for programming and control. Both the B8ZS and HDB3 encoding and decoding functions are selectable as well as AMI. An on-chip crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83SL34 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. It supports internal impedance matching for 75 Ω, 100 Ω, 110Ω and 120Ω for both transmitter and receiver. In the absence of the power supply, the transmit outputs and receive inputs are tri-stated allowing for redundancy applications The chip includes an integrated programmable clock multiplier that can synthesize T1 or E1 master clocks from a variety of external clock sources. APPLICATIONS • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interface • CSU/DSU E1/T1/J1 Interface • T1/E1/J1 LAN/WAN Routers • Public switching Systems and PBX Interfaces • T1/E1/J1 Multiplexer and Channel Banks Features (See Page 2) FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL34 T1/E1/J1 LIU (HOST MODE) O ne of four channels, CHANNEL_n - (n= 0:3) HW /HO ST WR_R/W RD_DS ALE-A S CS RDY _DTA CK INT ICT TPO S_n/TDATA _n TNE G_n/CO DES _n TCLK _n RCLK _n RNE G_n/LCV _n RP OS_n/RDATA _n RLOS _n RTIP_n RRING_n MAST ER CLO CK S YNT H ESIZER QRSS PATTER N GEN ERAT O R DMO _n TTIP_n TRING _n TXON_n HDB 3/ B8ZS ENCO DER T X /R X JIT T ER AT T ENUAT O R TIMIN G CO NT R O L TX FILTER & PUL SE SHAPER LINE DRIVER DRIVE MON IT O R L O CAL ANAL OG LO O PBACK REM OT E L O OPBACK DIGIT AL LO OPBACK HDB 3/ B8ZS DECO DER T X /R X JIT T ER AT T ENUAT O R TIMING & DAT A REC O VERY PEAK DET ECT O R & SLICER QRSS DET ECT OR NE T W OR K LOO P DET ECT OR RX EQ UALIZ ER EQ UALIZ ER CONT RO L AIS DET EC T O R LO S DET EC T O R L BO [3:0] LO O PBACK ENABL E NL CD EN AB LE Q RSS ENABL E µPTS1 µPTS2 D[7:0] µPCLK A[7:0] RE SET MIC RO PRO CESSO R CO NT RO LL ER T EST DF M TAO S ENABL E MCLK E1 MCLK T1 MCLKO UT |
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Similar Description - XRT83SL34 |
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