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XRT85L61 Datasheet(PDF) 1 Page - Exar Corporation

Part # XRT85L61
Description  BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT85L61 Datasheet(HTML) 1 Page - Exar Corporation

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Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
FEBRUARY 2004
REV. 1.0.1
GENERAL DESCRIPTION
The XRT85L61 is an integrated E1, T1, 64KHz
Centralized Clock interface for T1 (1.544Mbps) 100
Ω,
E1 (2.048Mbps) 75
Ω or 120Ω applications.
The XRT85L61 extracts either 2048kHz or 1544 kHz
clock signals from an E1 (2.048 MHz), T1 (1.544
Mhz) inputs respectively or 64 KHz, 8kHz or 400 Hz
clock signals from the 64kHz reference clock input.
The XRT85L61 includes an on-chip crystal-less jitter
attenuator with 32 bit FIFO that can either be enabled
or disabled.
FEATURES
Fully integrated single chip solution for E1,T1 or 64
kHz clock synchronization applications.
Extracts 2048 kHz, 1544 kHz clock and data com-
ponents
Extracts 64 KHz and 8 kHz, 400 Hz clock informa-
tion
Line Code Violation alarms
On-chip digital clock recovery circuit
Supports 75Ω and 120Ω (E1), 100Ω (T1) applica-
tions.
Crystal-less digital jitter attenuator with 32-bit FIFO
that can either be enabled or disabled
Receive loss of signal (RLOS) output
Meets Telcordia GR-1244-CORE Section 3.4.1 R3-
27 specification
Meets or exceeds T1 and E1 specifications in ITU
G.703, G.775
Single +3.3V Supply Operation
Logic inputs accept either 3.3 V or 5 V levels
28 pin TSSOP package
APPLICATIONS
Universal Clock Synchronization for G.703 Telecom
Formats
T1/E1 Line Receiver with Clock and Data Recovery
DSLAM
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61
Master Clock
Generator
Rx
Equalizer
MCLK1
(1.544 MHz for T1)
MCLK2
(2.048 MHz for E1
or 64 kbps)
Reference Inputs
RTIP
RRING
Line Side
Peak Detector
and Slicer
Clock and
Data
Recovery
Jitter
Attenuator
Clock
Extractor
Line code
and clock
violation
Detector
RPOS
RNEG
RCLK
(64kHz,1544kHz or 2048kHz)
8 kHz (for 64 kbps)
400 Hz (for 64 kbps)
RCLK_LCV/AIS
8 kHz_LCV/BPV
400 Hz_LCV
LOS
Detector
RLOS
Mode Select
T1, E1 or 64 kbps
S1
S2
S3
(T1 or E1 or 64 kbps input)
JAEN
DATAMUT
DATA_INV
RCLKINV


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