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TM2SN64EPU-12A Datasheet(PDF) 4 Page - Texas Instruments |
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TM2SN64EPU-12A Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 16 page  TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 dual-in-line memory module and components The dual-in-line memory module and components include: D PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage D Bypass capacitors: Multilayer ceramic D Contact area: Nickel plate and gold plate over copper functional block diagram for the TM2SN64EPU 8 DQ[0:7] 8 CS U0 CS U4 R R S0 DQMB0 DQ[0:7] DQMB4 DQ[32:39] DQM DQ[0:7] DQM RAS RAS: SDRAM U[0:7] CK0 CK: U1, U5 CK2 C SPD EEPROM SA0 SA1 SA2 A0 A1 A2 SCL SDA 8 DQ[0:7] 8 CS U1 CS U5 R R DQMB1 DQ[8:15] DQMB5 DQ[40:47] DQM DQ[0:7] DQM R = 10 Ω RC = 10 Ω C = 10 pF 8 DQ[0:7] 8 CS U2 CS U6 R R S2 DQMB2 DQ[16:23] DQMB6 DQ[48:55] DQM DQ[0:7] DQM 8 DQ[0:7] 8 CS U3 CS U7 R R DQMB3 DQ[24:31] DQMB7 DQ[56:63] DQM DQ[0:7] DQM CAS CAS: SDRAM U[0:7] WE WE: SDRAM U[0:7] CKE0 CKE: SDRAM U[0:7] A[0:11] A[0:11]: SDRAM U[0:7] RC RC RC VDD VSS Two 0.1 µF (minimum) per SDRAM U[0:7] U[0:7] CK1 CK: U2, U6 CK: U3, U7 CK3 C RC RC RC CK: U0, U4 LEGEND: CS = Chip select SPD = Serial Presence Detect |
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