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CY7C1041AV33/
GVT73256A16
PRELIMINARY
5
Low VCC Data Retention Waveform
Switching Waveforms
Read Cycle No. 1[11, 12]
Read Cycle No. 2[7, 11, 13, 14]
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected. Chip Enable and Output Enables are held in their active state.
13. Address valid prior to or coincident with latest occurring chip enable.
14. Chip Enable and Write Enable can initiate and terminate a write cycle.
V
CC
CE#
DATA RETENTION MODE
V
DR
3.0V
3.0V
V
IH
V
IL
t
RC
t
CDR
ADDR
VALID
tRC
DATA VALID
tOH
tAA
PREVIOUS DATA VALID
Q
CE#
tRC
DATA VALID
tLZCE
tACE
OE#
HIGH Z
tAOE
tLZOE
tHZCE
tHZOE
BLE#
BHE#
Q
UNDEFINED
DON'T CARE
tHZBE
tLZBE
tABE
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