48SD1616

4

All data sheets are subject to change without notice

©2005 Maxwell Technologies

All rights reserved.

256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM

01.07.05 REV 4

Standby Current in Power Down

I

CC2PS

CKE = V

IL

t

1, 2, 3

2

mA

I

CC2N

CKE, CS = V

IH

t

1, 2, 3

20

mA

Standby Current in non power down

I

CC2NS

CKE = V

IH

t

1, 2, 3

9

mA

Active standby current in power

I

CC3P

CKE = V

IL

t

1, 2, 3

4

mA

Active standby current in power down

I

CC3PS

CKE = V

IL

t

1, 2, 3

3

mA

Active standby power in non power

I

CC3N

CKE, CS = V

IN

t

1, 2, 3

30

mA

Active standby current in non power

I

CC3NS

CKE = V

IH

t

1, 2, 3

15

mA

CAS Latency = 2

CAS Latency = 3

I

CC4

t

BL = 4

1, 2, 3

110

145

mA

I

CC5

t

1, 2, 3

220

mA

I

CC6

V

V

1, 2, 3

3

mA

Input Leakage Current

I

LI

0<V

1, 2, 3

-1

1

uA

Output Leakage Current

I

LO

0<VOUT<V

CC

1, 2, 3

-1.5

1.5

uA

Output high voltage

V

OH

I

1, 2, 3

2.4

V

Output low voltage

V

OL

I

1, 2, 3

0.4

V

1. I

2. One Bank operation.

3. Input signals are changed once per one clock.

4. After power down mode, CLK operating current.

5. After power down mode, no CLK operating current.

6. Input signals are changed once per two clocks.

7. Input signals are V

8. Input signals are changed once per four clocks.

9. After self refresh mode set, self refresh current. Self refresh should only be used at temperatures below 70 °C.

(V