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28C256TRT1FE-12 Datasheet(PDF) 1 Page - Maxwell Technologies

Part # 28C256TRT1FE-12
Description  256K EEPROM (32K x 8-Bit) EEPROM
Download  14 Pages
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Manufacturer  MAXWELL [Maxwell Technologies]
Direct Link  http://www.maxwell.com
Logo MAXWELL - Maxwell Technologies

28C256TRT1FE-12 Datasheet(HTML) 1 Page - Maxwell Technologies

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All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301- www.maxwell.com
256K EEPROM (32K x 8-Bit)
28C256T
©2001 Maxwell Technologies
All rights reserved.
EEPROM
02.18.02 Rev 5
FEATURES:
•RAD-PAK® radiation-hardened against natural space radia-
tion
• Total dose hardness:
- > 100 Krad (Si), dependent upon space mission
• Excellent Single Event Effects:
- SEL
TH LET: > 120 MeV/mg/cm
2
- SEU
TH LET (read mode): > 90 MeV/mg/cm
2
- SEU
TH LET (write mode): > 18 MeV/mg/cm
2
• Package:
- 28 pin RAD-PAK® flat pack
- 28 pin RAD-PAK® DIP
- JEDEC approved byte wide pinout
• High Speed:
- 120, 150 ns maximum access times available
• High endurance:
- 10,000 erase/write (in Page Mode), 10-year data
retention
• Page Write Mode:
- 1 to 64 bytes
• Low power dissipation:
- 15 mA active current (cycle = 1 µ s)
- 20 µ A standby current (CE = V
CC)
DESCRIPTION:
Maxwell Technologies’ 28C256T high density 256k-bit
EEPROM microcircuit features a greater than 100 krad (Si)
total dose tolerance, depending upon space mission. The
28C256T is capable of in-system electrical byte and page pro-
grammability. It has a 64-Byte page programming function to
make its erase and write operations faster. It also features
data polling to indicate the completion of erase and program-
ming operations.
Maxwell Technologies' patented RAD-PAK® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
OE, CE, and WE
LOGIC
Y DECODER
X DECODER
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
IDENTIFICATION
OE
WE
CE
ADDRESS
INPUTS
V
CC
GND
DATA INPUTS/OUTPUTS
I/O0 - I/O7
Logic Diagram


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