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89LV1632RPQH-30 Datasheet(PDF) 8 Page - Maxwell Technologies |
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89LV1632RPQH-30 Datasheet(HTML) 8 Page - Maxwell Technologies |
8 / 12 page 8 All data sheets are subject to change without notice ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 08.18.05 REV 3 FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (2) (OE LOW FIIXED) FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3) (CS CONTROLLED) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low. A write ends at the earliest transition CS going high or WE going high. t WP is measured from the beginning of write to the end of write. 3. t CW is measured from the later of CS going low to end of write. 4. t AS is measured from the address valid to the beginning of write. 5. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write cycle. 8. If CS foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. D OUT is the read data of the new address. 10.When CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. |
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