®

1/17/05, V 1.2

Alliance Semiconductor

P. 4 of 18

AS7C252MNTD18A

Functional description

The AS7C252MNTD18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as

2,097,152 words × 18 bits and incorporates a LATE LATE Write.

operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address

are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead'

cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random

access or read-modify-write operations.

flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes.

Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock

cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for

normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined

mode, a two cycle deselect latency allows pending read or write operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W

pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including

burst, can be stalled using the CEN=1, the clock enable input.

TQFP package.

TQFP Capacitance

*Guaranteed not tested

TQFP thermal resistance

Parameter

Symbol

Test conditions

Min

Max

Unit

Input capacitance

-

5

pF

I/O capacitance

-

7

pF

Description

Conditions

Symbol

Typical

Units

Thermal resistance

1 This parameter is sampled

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer

40

°C/W

4–layer

22

°C/W

Thermal resistance

8

°C/W