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AS7C331MPFD18A-166TQCN Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C331MPFD18A-166TQCN Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
1 / 19 page February 2005 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C331MPFD18A 2/10/05, v. 1.3 Alliance Semiconductor 1 of 19 3.3V 1M x 18 pipelined burst synchronous SRAM Features • Organization: 1,048,576 x18 bits • Fast clock speeds to 166MHz • Fast clock to data access: 3.4/3.8 ns •Fast OE access time: 3.4/3.8 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output enable control • Available 100-pin TQFP package • Individual byte write and global write • Multiple chip enables for easy expansion • 3.3 V core power supply • 2.5 V or 3.3V I/O operation with separate VDDQ • Linear or interleaved burst control • Common data inputs and data outputs • Snooze mode for reduced power-standby Logic block diagram Selection guide -166 -133 Units Minimum cycle time 6 7.5 ns Maximum clock frequency 166 133 MHz Maximum clock access time 3.4 3.8 ns Maximum operating current 290 270 mA Maximum standby current 90 80 mA Maximum CMOS standby current (DC) 60 60 mA Burst logic ADV ADSC ADSP CLK LBO CLK CLR CS 20 18 20 A[19:0] 20 Address D Q CS CLK register 1M x 18 Memory array 18 18 DQb CLK DQ Byte Write registers DQa CLK DQ Byte Write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down DQ[a,b] 2 CE0 CE1 CE2 BWb BWa OE ZZ OE CLK CLK BWE GWE 18 |
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