2/10/05, v.1.1

Alliance Semiconductor

5 of 19

AS7C331MPFD32A

AS7C331MPFD36A

®

Signal descriptions

Snooze Mode

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

Pin

I/O

Properties

Description

CLK

I

CLOCK

Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.

A,A0,A1

I

SYNC

Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.

DQ[a,b,c,d]

I/O

SYNC

Data. Driven as output when the chip is enabled and when OE is active.

CE0

ISYNC

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,

ADSP is blocked. Refer to the “Synchronous truth table” for more information.

CE1, CE2

ISYNC

Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when

ADSC is active or when CE0 and ADSP are active.

ADSP

I

SYNC

Address strobe processor. Asserted low to load a new address or to enter standby mode.

ADSC

I

SYNC

Address strobe controller. Asserted low to load a new address or to enter standby mode.

ADV

I

SYNC

Advance. Asserted low to continue burst read/write.

GWE

ISYNC

Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d]

control write enable.

BWE

I

SYNC

Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.

BW[a,b,c,d]

ISYNC

Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of

BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,

the cycle is a read cycle.

OE

I

ASYNC

Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.

LBO

ISTATIC

driven Low, device follows linear Burst order. This signal is internally pulled High.

ZZ

I

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

NC

-

-

No connect