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AS7C3364PFS36B-166TQI Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation

Part # AS7C3364PFS36B-166TQI
Description  3.3V 64K X 32/36 pipeline burst synchronous SRAM
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C3364PFS36B-166TQI Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation

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AS7C3364PFS32B
AS7C3364PFS36B
®
12/10/04; v.1.4
Alliance Semiconductor
P. 6 of 19
Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b, c, d;
BWE, BWn = internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function
GWE
BWE
BWa
BWb
BWc
BWd
Write All Bytes
L
X
XXX
X
H
LLL
LL
Write Byte a
HL
LH
H
H
Write Byte c and d
HLH
H
L
L
Read
HH
XXX
X
H
L
HHH
H
Operation
ZZ
OE
I/O Status
Snooze mode
H
X
High-Z
Read
L
L
Dout
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Interleaved burst address (LBO = 1)
Linear burst address (LBO = 0)
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
1st Address
0 00 11 0
1 1
1st Address
0 0
0 11 01 1
2nd Address
0 10 01 1
1 0
2nd Address
0 1
1 01 10 0
3rd Address
1 01 10 0
0 1
3rd Address
1 0
1 10 00 1
4th Address
1 11 00 1
0 0
4th Address
1 1
1 00 11 0


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