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AS7C32096A-20TCN Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation |
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AS7C32096A-20TCN Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation |
6 / 9 page ® AS7C32096A 2/24/05, v. 1.0 Alliance Semiconductor P. 6 of 9 Write waveform 2 (CE controlled)9 AC test conditions Notes 1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. 2 For test conditions, see AC Test Conditions. 3tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage. 4 This parameter is guaranteed, but not tested. 5WE is HIGH for read cycle. 6CE and OE are LOW for read cycle. 7 Address valid prior to or coincident with CE transition Low. 8 All read cycle timings are referenced from the last valid address to the first transitioning address. 9 All write cycle timings are referenced from the last valid address to the first transitioning address. 10 C=30pF, except on High Z and Low Z parameters, where C=5pF. tAW Address CE WE DOUT tCW tWP tDW tDH tAH tWZ tWC tAS Data valid DIN tWR 350 Ω C10 320 Ω DOUT GND +3.3V Figure B: 3.3V Output load - Output load: see Figure B. - Input pulse level: GND to 3.0V. See Figures A and B. - Input rise and fall times: 2 ns. See Figure A. - Input and output timing reference levels: 1.5V. 168 Ω Thevenin equivalent: DOUT +1.728V 10% 90% 10% 90% GND +3.0V Figure A: Input pulse 2 ns |
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