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AS7C25512NTF36A-10TQCN Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C25512NTF36A-10TQCN Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
1 / 18 page April 2005 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C25512NTF32A AS7C25512NTF36A 4/21/05, v 1.2 Alliance Semiconductor P. 1 of 18 2.5V 512K × 32/36 Flowthrough Synchronous SRAM with NTDTM Features • Organization: 524,288 words × 32 or 36 bits •NTD™ architecture for efficient bus operation • Fast clock to data access: 7.5/8.5/10 ns •Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable control • Available in 100-pin TQFP package • Individual byte write and global write • Clock enable for operation hold • Multiple chip enables for easy expansion • 2.5V core power supply • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Logic block diagram Selection guide -75 -85 -10 Units Minimum cycle time 8.5 10 12 ns Maximum clock access time 7.5 8.5 10 ns Maximum operating current 275 250 230 mA Maximum standby current 90 80 80 mA Maximum CMOS standby current (DC) 60 60 60 mA Address D Q CLK register Output Buffer DQ[a,b,c,d] 19 19 CLK CE0 CE1 CE2 A[18:0] OE CEN Control CLK logic Data D Q CLK Input Register 32/36 32/36 OE 512K x 32/36 SRAM Array R/W DQ[a,b,c,d] BWb BWd CLK Q D ADV / LD LBO Burst logic addr. registers Write delay 19 ZZ CLK 32/36 32/36 32/36 32/36 BWc BWa |
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