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AS7C31025B-10JCN Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C31025B-10JCN Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
1 / 9 page March 2004 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C31025B 3.3V 128K X 8 CMOS SRAM (Center power and ground) 3/24/04, v. 1.3 Alliance Semiconductor P. 1 of 9 Features • Industrial and commercial temperatures • Organization: 131,072 x 8 bits • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Low power consumption: ACTIVE - 252 mW / max @ 10 ns • Low power consumption: STANDBY - 18 mW / max CMOS • 6 T 0.18 u CMOS technology • Easy memory expansion with CE, OE inputs • Center power and ground • TTL/LVTTL-compatible, three-state I/O • JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram 512 x 256 x 8 Array (1,048,576) Input buffer I/O0 I/O7 OE CE WE Column decoder Control circuit A0 A1 A2 A3 A4 A5 A6 A7 VCC GND A8 Pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5678 ns Maximum operating current 70 65 60 55 mA Maximum CMOS standby current 5555 mA |
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