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AS7C33128NTD32B-200TQC Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation |
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AS7C33128NTD32B-200TQC Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation |
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9 / 18 page  ® AS7C33128NTD32B AS7C33128NTD36B 2/8/05; v.1.5 Alliance Semiconductor P. 9 of 18 Snooze Mode Electrical Characteristics Timing characteristics over operating range Parameter Sym -200 -166 -133 Unit Notes1 1 See “Notes” on page 15. Min Max Min Max Min Max Clock frequency fMAX – 200 - 166 - 133 MHz Cycle time tCYC 5 – 6 - 7.5 - ns Clock access time tCD – 3.0 - 3.5 - 4.0 ns Output enable Low to data valid tOE – 3.0 - 3.5 - 4.0 ns Clock High to output Low Z tLZC 0 – 0 - 0 - ns 2,3,4 Data output invalid from clock High tOH 1.5–1.5 - 1.5 - ns 4 Output enable Low to output Low Z tLZOE 0 – 0 - 0 - ns 2,3,4 Output enable High to output High Z tHZOE – 3.0 - 3.5 - 4.0 ns 2,3,4 Clock High to output High Z tHZC – 3.0 - 3.5 - 4.0 ns 2,3,4 Clock High to output High Z tHZCN – 1.5 - 1.5 - 2.0 ns 5 Clock High pulse width tCH 2.0–2.4 - 2.5 - ns 6 Clock Low pulse width tCL 2.3–2.4 - 2.5 - ns 6 Address setup to clock High tAS 1.4–1.5 - 1.5 - ns 7 Data setup to clock High tDS 1.4–1.5 - 1.5 - ns 7 Write setup to clock High tWS 1.4–1.5 - 1.5 - ns 7 Chip select setup to clock High tCSS 1.4–1.5 - 1.5 - ns 7 Clock enable setup to clock High tCENS 1.4–1.5 - 1.5 - ns 7 ADV/LD setup to clock High tADVS 1.4–1.5 - 1.5 - ns 7 Address hold from clock High tAH 0.4–0.5 - 0.5 - ns 7 Data hold from clock High tDH 0.4–0.5 - 0.5 - ns 7 Write hold from clock High tWH 0.4–0.5 - 0.5 - ns 7 ADV/LD hold from clock High tADVH 0.4–0.5 - 0.5 - ns 7 Clock enable hold from clock High tCENH 0.4–0.5 - 0.5 - ns 7 Chip select hold from clock High tCSH 0.4–0.5 - 0.5 - ns 7 Description Conditions Symbol Min Max Units Current during Snooze Mode ZZ > VIH ISB2 30 mA ZZ active to input ignored tPDS 2cycle ZZ inactive to input sampled tPUS 2cycle ZZ active to SNOOZE current tZZI 2cycle ZZ inactive to exit SNOOZE current tRZZI 0cycle |
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