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ELANSC400-66AI Datasheet(PDF) 9 Page - Advanced Micro Devices |
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ELANSC400-66AI Datasheet(HTML) 9 Page - Advanced Micro Devices |
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9 / 132 page  Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet 9 High-Speed PLL .................................................................................................................... 81 Band Gap Block .................................................................................................................... 81 RTC Voltage Monitor ............................................................................................................. 81 Clock Specifications .............................................................................................................. 83 Absolute Maximum Ratings .......................................................................................................86 Operating Ranges ...................................................................................................................... 86 DC Characteristics Over Commercial and Industrial Operating Ranges .................................... 86 Capacitance ............................................................................................................................... 87 Typical Power Numbers ............................................................................................................. 88 Power Requirements Under Different Power Management Modes ...................................... 88 Derating Curves ......................................................................................................................... 89 AC Switching Characteristics and Waveforms .......................................................................... 91 Key to Switching Waveforms ................................................................................................ 91 AC Switching Test Waveforms .................................................................................................. 91 AC Switching Characteristics over Commercial and Industrial Operating Ranges ............... 92 Thermal Characteristics ........................................................................................................... 130 Physical Dimensions—BGA 292—Plastic Ball Grid Array ...................................................... 131 LIST OF FIGURES Figure 1. Typical Mobile Terminal Design ............................................................................. 21 Figure 2. System Diagram with Trade-offs—ÉlanSC400 Microcontroller ............................. 22 Figure 3. System Design with Trade-offs—ÉlanSC410 Microcontroller ............................... 23 Figure 4. Clock Generation Block Diagram ........................................................................... 76 Figure 5. Clock Source Block Diagram ................................................................................. 78 Figure 6. 32-kHz Crystal Circuit ............................................................................................ 79 Figure 7. 32-kHz Oscillator Circuit ........................................................................................ 79 Figure 8. Intermediate and Low-Speed PLLs Block Diagram ............................................... 80 Figure 9. Graphics Dot Clock PLL Block Diagram ................................................................ 81 Figure 10. High-Speed PLL Block Diagram ............................................................................ 82 Figure 11. RTC Voltage Monitor Circuit .................................................................................. 82 Figure 12. Timing Diagram for RTC-On Power-Down Sequence ........................................... 83 Figure 13. PLL Enabling Timing Sequence ............................................................................ 85 Figure 14. 3.3-V I/O Drive Type A Rise Time ......................................................................... 89 Figure 15. 3.3-V I/O Drive Type A Fall Time ........................................................................... 89 Figure 16. 3.3-V I/O Drive Type B Rise Time ......................................................................... 89 Figure 17. 3.3-V I/O Drive Type B Fall Time ........................................................................... 89 Figure 18. 3.3-V I/O Drive Type C Rise Time ......................................................................... 90 Figure 19. 3.3-V I/O Drive Type C Fall Time ........................................................................... 90 Figure 20. 3.3-V I/O Drive Type D Rise Time ......................................................................... 90 Figure 21. 3.3-V I/O Drive Type D Fall Time ........................................................................... 90 Figure 22. 3.3-V I/O Drive Type E Rise Time ......................................................................... 90 Figure 23. 3.3-V I/O Drive Type E Fall Time ........................................................................... 90 Figure 24. Power-Up Timing Sequence .................................................................................. 92 Figure 25. Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle .................................... 94 Figure 26. Fast Mode CPU Read of Three Consecutive Bytes from 8-Bit ROM/Flash Memory .. 95 Figure 27. Fast Mode 8-/16-/32-Bit Flash Memory Write Cycles ............................................ 95 Figure 28. Fast Mode 16-Bit Burst ROM Read Cycles ........................................................... 96 Figure 29. Fast Mode CPU Burst Read from 32-Bit Burst Mode ROM/Flash Memory ........... 96 Figure 30. Normal Mode 8-/16-Bit ROM/Flash Memory Read Cycles .................................... 97 Figure 31. Normal Mode 8-/16-Bit Flash Memory Write Cycles .............................................. 97 Figure 32. DRAM Page Hit Read, Interleaved ........................................................................ 99 Figure 33. DRAM Page Hit Write, Interleaved ........................................................................ 99 Figure 34. DRAM Page Miss Read, Interleaved ................................................................... 100 |
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