®

AS7C33128NTD32B

AS7C33128NTD36B

2/8/05; v.1.5

Alliance Semiconductor

P. 5 of 18

Snooze Mode

MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

Burst order

Signal

I/O

Properties Description

CLK

I

CLOCK

Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.

CEN

I

SYNC

Clock enable. When de-asserted high, the clock input signal is masked.

A, A0, A1

I

SYNC

Address. Sampled when all chip enables are active and ADV/LD is asserted.

DQ[a,b,c,d]

I/O

SYNC

Data. Driven as output when the chip is enabled and OE is active.

CE0, CE1,

CE2

ISYNC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are

ignored when ADV/LD is high.

ADV/LD

ISYNC

Advance or Load. When sampled high, the internal burst address counter will increment in the

order defined by the LBO input value. When low, a new address is loaded.

R/W

ISYNC

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE

operation. Is ignored when ADV/LD is high.

BW[a,b,c,d]

ISYNC

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE

command and BURST WRITE.

OE

I

ASYNC

Asynchronous output enable. I/O pins are not driven when OE is inactive.

LBO

ISTATIC

driven Low, device follows linear Burst order. This signal is internally pulled High.

ZZ

I

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

NC

-

-

No connect

Interleaved burst order (LBO = 1)

Linear burst order (LBO = 0)

A1 A0

A1 A0

A1 A0

A1 A0

A1 A0

A1 A0

A1 A0

A1 A0

Starting address

0 00 11 0

1 1

Starting Address

0 00 11 01 1

First increment

0 1

0 0

1 1

1 0

First increment

0 1

1 0

1 1

0 0

Second increment

1 0

1 1

0 0

0 1

Second increment

1 0

1 1

0 0

0 1

Third increment

1 1

1 0

0 1

0 0

Third increment

1 1

0 0

0 1

1 0