®

AS7C33128PFD32B

AS7C33128PFD36B

1/31/05; v.1.1

Alliance Semiconductor

P. 11 of 19

Key to switching waveforms

Timing waveform of read cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.

*Outputs are disabled within two clk cycles after DSEL command

don’t care

Falling input

Rising input

Undefined

CE1

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

ADV

OE

Dout

LOAD NEW ADDRESS

ADV inserts wait states

Q(A2Ý10)

Q(A2Ý11)

Q(A3)

Q(A2)

Q(A2Ý01)

Q(A3Ý01)

Q(A3Ý10)

Q(A1)

A2

A1

A3

Read

Q(A1)

Suspend

Read

Q(A1)

Read

Q(A2)

Burst

Read

Q(A 2Ý01)

Read

Q(A3)

DSEL*

Burst

Read

Q(A 2Ý10)

Suspend

Read

Q(A 2Ý10)

Burst

Read

Q(A 2Ý11)

Burst

Read

Q(A 3Ý01)

Burst

Read

Q(A 3Ý10)

Burst

Read

Q(A 3Ý11)