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PM49FL002T-33VC Datasheet(PDF) 7 Page - PMC-Sierra, Inc |
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PM49FL002T-33VC Datasheet(HTML) 7 Page - PMC-Sierra, Inc |
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7 / 46 page  Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4 PMC Pm49FL002 / 004 7 The Pm49FL002/004 provide three levels of data protec- tion for the critical BIOS code of PC and Notebook. It includes memory hardware write protection, hardware data protection and software data protection. MEMORY HARDWARE WRITE PROTECTION The Pm49FL002 has a 16 Kbyte top boot block and the Pm49FL004 has a 64 Kbyte top boot block. When work- ing in-system, the memory hardware write protection fea- ture can be activated by two control pins - Top Block Lock (TBL#) and Write Protection (WP#) for both FWH and LPC modes. When TBL# is pulled low (V IL), the boot block is hardware write protected. A sector erase, block erase, or byte program command attempts to erase or program the boot block will be ignored. When WP# is pulled low (V IL), the Block 0 ~ Block 14 of Pm49FL002, or the Block 0 ~ Block 6 of Pm49FL004 (except the boot block) are hardware write protected. Any attemp to erase or program a sector or block within this area will be ig- nored. Both TBL# and WP# pins must be set low (V IL) for pro- tection or high (V IH) for un-protection prior to a program or erase operation. A logic level change on TBL# or WP# pin during a program or erase operation may cause un- predictable results. The TBL# and WP# pins work in combination with the block locking registers. When active, these pins write protect the appropriate blocks regardless of the associ- ated block locking registers setting. HARDWARE DATA PROTECTION Hardware data protection protects the devices from un- intentional erase or program operation. It is performed by the devices automatically in the following three ways: (a) VCC Detection: if VCC is below 1.8 V (typical), the program and erase functions are inhibited. (b) Write Inhibit Mode: holding any of the signal OE# low, or WE# high inhibits a write cycle (A/A Mux mode only). (c) Noise/Glitch Protection: pulses of less than 5 ns (typi- cal) on the WE# input will not initiate a write cycle (A/A Mux mode only). DEVICE OPERATION (CONTINUED) SOFTWARE DATA PROTECTION The devices feature a software data protection function to protect the device from an unintentional erase or pro- gram operation. It is performed by JEDEC standard Soft- ware Data Protection (SDP) command sequences. See Table 14 for SDP Command Definition. A program op- eration is initiated by three memory write cycles of un- lock command sequence. A chip (only available in A/A Mux mode), sector or block erase operation is initiated by six memory write cycles of unlock command se- quence. During SDP command sequence, any invalid command or sequence will abort the operation and force the device back to standby mode. BYTE PROGRAMMING In program operation, the data is programmed into the devices (to a logical “0”) on a byte-by-byte basis. In FWH and LPC modes, a program operation is activated by writing the three-byte command sequence and program address/data through four consecutive memory write cycles. In A/A Mux mode, a program operation is acti- vated by writing the three-byte command sequence and program address/data through four consecutive bus cycles. The row address (A10 - A0) is latched on the falling edge of R/C# and the column address (A21 - A11) is latched on the rising edge of R/C#. The data is latched on the rising edge of WE#. Once the program operation is started, the internal control logic automatically handles the internal programming voltages and timing. A data “0” can not be programmed back to a “1”. Only erase operation can convert “0”s to “1”s. The Data# Poll- ing on I/O7 or Toggle Bit on I/O6 can be used to detect when the programming operation is completed in FWH, LPC, and A/A Mux modes. CHIP ERASE The entire memory array can be erased by chip erase operation available under the A/A Mux mode operated by EPROM Programmer only. Pre-programs the device is not required prior to the chip erase operation. Chip erase starts immediately after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The Data# Polling on I/O7 or Toggle Bit on I/O6 can be used to detect the progress or completion of erase operation. The devices will return back to standy mode after the completion of chip erase. |
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