AS7C33512PFD18A-166TQI datasheet(1/20 Pages) ALSC

Part #	AS7C33512PFD18A-166TQI

Description	3.3V 512K x 18 pipeline burst synchronous SRAM

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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November 2004

®

AS7C33512PFD18A

3.3V 512K

× 18 pipeline burst synchronous SRAM

12/1/04;

v.1.3

Alliance Semiconductor

1 of 20

Features

• Organization: 524,288 words × 18 bits

• Fast clock speeds to 166 MHz

• Fast clock to data access: 3.5/4.0 ns

•Fast OE access time: 3.5/4.0 ns

• Fully synchronous register-to-register operation

• Dual-cycle deselect

• Asynchronous output enable control

• Individual byte write and global write

• Available in 100-pin TQFP package

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

• Byte write enables

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate VDDQ

Selection guide

–166

–133

Units

Minimum cycle time

6

7.5

ns

Maximum clock frequency

166

133

MHz

Maximum clock access time

3.5

4

ns

Maximum operating current

475

425

mA

Maximum standby current

130

100

mA

Maximum CMOS standby current (DC)

30

mA

Logic block diagram

Burst logic

ADV

ADSC

ADSP

CLK

LBO

CLK

CLR

CS

19

17

19

A[18:0]

19

Address

D

Q

CS

CLK

register

512K × 18

Memory

array

18

DQb

CLK

DQ

Byte Write

registers

DQa

CLK

DQ

Byte Write

registers

Enable

CLK

DQ

register

Enable

CLK

DQ

delay

register

CE

Output

registers

Input

registers

Power

down

2

CE0

CE1

CE2

BWb

BWa

OE

ZZ

OE

CLK

BWE

GWE

18

DQ[a,b]

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AS7C33512PFD18A-166TQI Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

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