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AS9C25256M2036L-166FI Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation |
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AS9C25256M2036L-166FI Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation |
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7 / 30 page  AS9C25256M2036L AS9C25128M2036L 9/30/04, v.1.3 Alliance Semiconductor P. 7 of 30 ® Signal description Notes: 1. Subscript 'x' represents 'A' for Port A and 'B' for Port B. 2. OPTx,VDDQx and VDD must be set to appropriate operating levels before applying inputs on the I/Os and controls for that port. 3. OPTx = VDD (2.5V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 3.3V level and VDDQx must be supplied at 3.3V. OPTx = VSS (0V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 2.5V level and VDDQx must be supplied at 2.5V. Each port can independently operate on either of the VDDQ levels. 4. If unused JTAG inputs may be left unconnected. 5. JTAG is not supported in PQFP package. 6. Address A17 is a NC forAS9C25128M2036L Signal I/O Properties Description Notes Port A Port B CLKA CLKB ICLOCK Clock. Each port has an independent Clock input that can be of different frequencies. All inputs except OEx and ZZx are synchronous to the corresponding port’s clock and must meet setup and hold time about the rising edge of the clock. 1 A0A - A17A A0B - A17B I SYNC External Address. Sampled on the rising edge of corresponding port clock 6 DQ0A - DQ35A DQ0B - DQ35B I/O SYNC Bidirectional data pins CE0A, CE1A CE0B, CE1B I SYNC Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of corresponding port clock. R/WA R/WB I SYNC Read/Write enable. Drive this pin LOW to write to, or HIGH to Read from the memory array. BE0A - BE3A BE0B - BE3B I SYNC Byte Enable Inputs. Active low. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. (Refer Byte Control Truth Table) ADSA ADSB I SYNC Address Strobe Enable.Active low. Loads external address onto the counter. (Refer Counter Control Truth Table) INCA INCB I SYNC Address Counter Increment. Active low. Increments the counter value. (Refer Counter Control Truth Table) RPTA RPTB I SYNC Address Counter Repeat. Active low. Reloads the counter with the previously loaded external address.(Refer Counter Control Truth Table) OEA OEB I ASYNC Asynchronous output enable. I/O pins are driven when the OE is low and the chip is in Read mode. A high on OE tristates the I/O pins. ZZA ZZB I ASYNC Snooze Mode Input. Places the device in low power mode. Data is retained. This pin has an internal pull-down and can be floating. PL/FTA PL/FTB ISTATIC Pipeline/Flow-Through Select. When low, enables single register flow-through mode. When high, enables double register Pipeline mode. This pin has an internal pull-up and can be left floating to operate in pipeline mode. OPTA OPTB ISTATIC VDDQx Option. OPTx selects the operating voltage levels for the I/Os, addresses, clock, and controls on that port. This pin has an internal pull-up and can be left floating to operate in 3.3V mode. 1,2,3 INTA INTB O SYNC Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic Truth Table) COLA COLB O SYNC Collision Alert Flag. Used to indicate collision during simultaneous memory access to the same location by both the ports (Refer Collision Detection Truth Table) VDDQA VDDQB IPOWER Power to I/O bus. Can be 3.3V or 2.5V depending on OPTx input. 1,2,3 VDD I POWER Power Inputs (To be connected to 2.5V Power supply) 2 VSS I GROUND Ground Inputs (To be connected to Ground supply) TCK I CLOCK (JTAG) JTAG Test Clock Input. All JTAG signals except TRST are synchronous to this clock. 4,5 TDI I SYNC (JTAG) JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. 4,5 TDO O SYNC (JTAG) JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally tristated except when the captured data is shifted out of the JTAG TAP. 5 TMS I SYNC (JTAG) JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. 4,5 TRST I ASYNC (JTAG) JTAG Test Reset Input. Asynchronous input used to initialize TAP controller. 4,5 |
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