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ASM2I20805AG-20-AT Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

Part # ASM2I20805AG-20-AT
Description  2.5V CMOS Dual 1-To-5 Clock Driver
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

ASM2I20805AG-20-AT Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation

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June 2005
ASM2P20805A
rev 0.2
Alliance Semiconductor
2575, Augustine Drive
• Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V CMOS Dual 1-To-5 Clock Driver
Features
Advanced CMOS Technology
Guaranteed low skew < 200pS (max.)
Very low propagation delay < 2.5nS (max)
Very low duty cycle distortion < 270pS (max)
Very low CMOS power levels
Operating frequency up to 166MHz
TTL compatible inputs and outputs
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
VCC = 2.5V ± 0.2V
Available in SSOP and QSOP packages
Block Diagram
Functional Description
The ASM2P20805A is a 2.5V Clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in
this
document.
The
ASM2P20805A
offers
low
capacitance inputs. The ASM2P20805A is designed for
high speed clock distribution where signal quality and skew
are critical. The ASM2P20805A also allows single point-to-
point transmission line driving in applications such as
address distribution, where one signal must be distributed
to multiple receivers with low skew and high signal quality.
Pin Diagram
OB1 – OB5
INA
INB
OEB
OEA
OA1 – OA5
MON
5
5
VCCB
OB1
OB2
OB3
GNDB
OB4
OB5
MON
OEB
INB
INA
OEA
GNDQ
OA5
OA4
GNDA
OA3
OA2
OA1
VCCA
A
S
M
2
P
2
0
8
0
5
A
10
11
9
12
8
13
7
14
6
15
5
16
4
17
3
18
2
19
1
20


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