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ASM3P2508SPF-08ST Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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ASM3P2508SPF-08ST Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 7 page February 2005 ASM3P2508SP rev 0.4 Clock Synthesizer and Frequency Generator with Peak EMI reduction 2 of 7 Notice: The information in this document is subject to change without notice. PWRDNB XOUT 1 2 3 4 5 6 7 8 ASM3P2508SP XIN/CLKIN Sys_REF_CLK PCI_CLK VSS T1_CLK VDD Pin Configuration Pin Description Pin# Pin Name Type Description 1 XIN/CLKIN I Crystal connection or external reference frequency input. This pin has dual functions. It can be connected either to an external crystal or an external reference clock. 2 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected. 3 VDD P Power supply for the entire chip 4 Sys_REF_CLK O PLL 1 output System Reference Clock @ 20MHz 5 PWRDNB I Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not used. Power -down Mode shuts off all the Outputs. 6 PCI_CLK O PLL 2 Spread spectrum clock output @ 33.33MHz 7 VSS P Ground to entire chip. Connect to system ground 8 T1_CLK O Reference output T1 Clock @ 25MHz Typical Modulation Profile Absolute Maximum Ratings Symbol Parameter Rating Unit VDD, VIN Voltage on any pin with respect to Ground -0.5 to +7.0 V TSTG Storage temperature -65 to +125 °C TA Operating temperature 0 to 70 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD 22- A114-B) 2 KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. |
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