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ASM3P623S00FG-16-ST Datasheet(PDF) 5 Page - Alliance Semiconductor Corporation |
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ASM3P623S00FG-16-ST Datasheet(HTML) 5 Page - Alliance Semiconductor Corporation |
5 / 16 page July 2005 ASM3P623S00A/B/C/D/E/F rev 1.0 Zero Cycle Slip Peak EMI Reduction IC 5 of 16 Notice: The information in this document is subject to change without notice. Operating Conditions for ASM3P623S00A/B/C and ASM3P623S00D/E/F Devices Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance 30 pF CIN Input Capacitance 7 pF Electrical Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F Parameter Description Test Conditions Min Typ Max Unit VIL Input LOW Voltage 5 0.8 V VIH Input HIGH Voltage 5 2.0 V IIL Input LOW Current VIN = 0V 50 µA IIH Input HIGH Current VIN = VDD 100 µA VOL Output LOW Voltage 6 IOL = 8mA 0.4 V VOH Output HIGH Voltage 6 IOH = -8mA 2.4 V IDD Supply Current Unloaded outputs 15 mA Zo Output Impedance 23 Ω Switching Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F 7 Parameter Description Test Conditions Min Typ Max Unit 1/t1 Output Frequency 30pF load 20 50 MHz Duty Cycle 6 = (t2 / t1) * 100 Measured at VDD/2 40 50 60 % t3 Output Rise Time 6 Measured between 0.8V and 2.0V 2.5 nS t4 Output Fall Time 6 Measured between 2.0V and 0.8V 2.5 nS t5 Output-to-output skew 6 All outputs equally loaded 250 pS t6 Delay, CLKIN Rising Edge to CLKOUT Rising Edge 6 Measured at VDD /2 ±350 pS t7 Device-to-Device Skew 6 Measured at VDD/2 on the CLKOUT pins of the device 700 pS tJ Cycle-to-cycle jitter 6 Loaded outputs 200 pS tLOCK PLL Lock Time 6 Stable power supply, valid clock presented on CLKIN pin 1.0 mS Notes: 5. CLKIN input has a threshold voltage of VDD/2 6. Parameter is guaranteed by design and characterization. Not 100% tested in production 7. All parameters specified with loaded outputs. |
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