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ASM5CVF857 Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation |
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ASM5CVF857 Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation |
4 / 15 page August 2004 ASM5CVF857 rev 1.2 2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz) 4 of 15 Notice: The information in this document is subject to change without notice. Pin Description Pin Number Pin Name Pin Type Pin Description 4, 11, 12, 15, 21, 28, 34, 38, 45 VDD P Power supply, 2.5V 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 GND P Ground. 16 AVDD P Analog power supply, 2.5V. 17 AGND P Analog ground. 27, 29, 39, 44, 46, 22, 20, 10, 5, 3 CLKT(9:0) O “True” clock of differential pair outputs. 26, 30, 40, 43, 47, 23, 19, 9, 6, 2 CLKC(9:0) O “Complementary” clocks of differential pair outputs. 14 CLK_INC I “Complementary” reference clock input. 13 CLK_INT I “True” reference clock input. 33 FB_OUTC O “Complementary” feedback output dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. 32 FB_OUTT O “True” feedback output dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. 36 FB_INT I “True” feedback input provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. 35 FB_INC I “Complementary” feedback input provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error. 37 PDB I Power down. LVCMOS input. |
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