July 2005

ASM5I961P

rev 0.2

Low Voltage Zero Delay Buffer

3 of 14

Notice: The information in this document is subject to change without notice.

Table 2: Function Table

Control

Default

0

1

F_RANGE

0

PLL high frequency range. ASM5I961P input

reference and output clock frequency range is

100 – 200 MHz

PLL low frequency range. ASM5I961P input

reference and output clock frequency range is

50 – 100 MHz

OE

¯¯

0

Outputs enabled

Outputs disabled (high–impedance state)

Table 3: Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Supply Voltage

–0.3

3.6

V

DC Input Voltage

–0.3

V

DC Output Voltage

–0.3

V

DC Input Current

±20

mA

DC Output Current

±50

mA

Storage Temperature Range

–40

125

°C

Static Discharge Voltage

(As per JEDEC STD 22- A114-B)

2

KV

Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

Input HIGH Voltage

2.0

V

LVCMOS

Input LOW Voltage

–0.3

0.8

V

LVCMOS

Peak–to–peak input voltage

1

¯¯¯¯¯¯¯¯¯¯

500

1000

mV

LVPECL

Common Mode Range

1

¯¯¯¯¯¯¯¯¯¯

1.2

V

LVPECL

Output HIGH Voltage

2.4

V

2

Output LOW Voltage

0.55

V

2

Output Impedance

14

20

Ω

Input Current

±120

mA

Input Capacitance

4.0

pF

Power Dissipation Capacitance

8.0

10

pF

Per Output

Maximum PLL Supply Current

2.0

5.0

mA

Maximum Quiescent Supply Current

mA

Output Termination Voltage

V

Notes:

2. The ASM5I961P is capable of driving 50

Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a