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Rev 1.0

July. 2002

K7Q163654A

K7Q161854A

Write cycles are initiated by activating W at the rising edge of the positive input clock K.

Address is presented and stored in the write address register synchronized with K clock.

For 4-bit burst DDR operation, it will write four 36-bit or 18-bit data words with each write command.

The first "late" data is transfered and registered in to the device synchronous with next K clock rising edge.

Next burst data is transfered and registered synchronous with following K clock rising edge.

The process continues until all four data are transfered and registered.

Continuous write operations are initated with K rising edge.

And "late writed" data is presented to the device on every rising edge of both K and K clocks.

The device disregards input data presented on the same cycle W disabled.

When the W is disabled after a read operation, the K7Q163654A and K7Q161854A will first complete burst read operation before

entering into deselect mode at the next K clock rising edge.

The K7Q163654A and K7Q161854A support byte write operations.

Write Operations

Programmable Impedance Output Buffer Operation

Single Clock Mode

Depth Expansion

The K7Q163654A and K7Q161854A can be used with the single clock pair K and K.

In this mode, C and C must be tied high during power up and this single clock pair control both the input and output registers.

C and C cannot be tied high during operation.

System flight time and clock skew could not be compensated in single clock mode.

Separate input and output ports enables easy depth expansion.

Each port can be selected and deselected independently

and read and write operation do not affect each other.

Before chip deselected, all read and write pending operations are completed.

The value of RQ (within 15%) is five times the output impedance desired.

For example, 250

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.

In all cases impedance updates are transparent to the user and do not produce access time "push-outs"

or other anomalous behavior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,

the SRAM needs 1024 non-read cycles.