ASM5I9350 datasheet(7/12 Pages) ALSC

Part #	ASM5I9350

Description	3.3V 1:10 LVCMOS PLL Clock Generator

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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7 / 12 page

July 2005

ASM5I9350

rev 0.2

3.3V 1:10 LVCMOS PLL Clock Generator

7 of 12

Notice: The information in this document is subject to change without notice.

AC Electrical Specifications (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1

Parameter

Description

Condition

Min

Typ

Max

Unit

fVCO

VCO Frequency

200

-

500

MHz

÷16 Feedback

12.5

-

31.25

÷32 Feedback

6.25

-

15.625

fin

Input Frequency

Bypass mode

(PLL_EN = 0)

0

-

200

MHz

fXTAL

Crystal Oscillator Frequency

10

-

25

MHz

frefDC

Input Duty Cycle

25

-

75

%

tr, tf

TCLK Input Rise/FallTime

0.8V to 2.0V

-

1.0

nS

÷2 Output

100

-

200

÷4 Output

50

-

125

fMAX

Maximum Output Frequency

÷8 Output

25

-

62.5

MHz

fMAX < 100 MHz

47.5

-

52.5

DC

Output Duty Cycle

fMAX > 100 MHz

45

-

55

%

tr, tf

Output Rise/Fall times

0.8V to 2.4V

0.1

-

1.0

nS

tsk(O)

Output-to-Output Skew

Banks at same voltage

-

150

pS

tsk(B)

Bank-to-Bank Skew

Banks at different voltages

-

350

pS

tPLZ, HZ

Output Disable Time

-

10

nS

tPZL, ZH

Output Enable Time

-

10

nS

÷16 Feedback

-

0.7 – 0.9

-

BW

PLL Closed Loop Bandwidth (–3dB)

÷32 Feedback

-

0.6 – 0.8

-

MHz

Same frequency

-

150

tJIT(CC)

Cycle-to-Cycle Jitter

Multiple frequencies

-

250

pS

Same frequency

-

100

tJIT(PER)

Period Jitter

Multiple frequencies

-

150

pS

tLOCK

Maximum PLL Lock Time

-

1

mS

Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.

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