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ASM5I9658-32-LR Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation |
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ASM5I9658-32-LR Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation |
7 / 14 page July 2005 ASM5I9658 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator 7 of 14 Notice: The information in this document is subject to change without notice. Figure 3. VCC_PLL Power Supply Filter ASM5I9658 Applications Information Driving Transmission Lines The ASM5I9658 supports output clock frequencies from 50 to 250MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500MHz for stable and optimal operation. Two operating frequency ranges are supported: 50 to 125MHz and 100 to 250 MHz. Table 7 illustrates the configurations supported by the ASM5I9658. PLL zero-delay is supported if BYPASS=1, PLL_EN=1 and the input frequency is within the specified PLL reference frequency range. Table 7: ASM5I9658 Configurations (QFB connected to FB_IN) Frequency BYPASS PLL_ EN VCO_ SEL Operation Ratio Output range (fQ0-7) VCO 0 X X Test mode: PLL and divider bypass fQ0-9 =fREF 0-250 MHz n/a 1 0 0 Test mode: PLL bypass fQ0-9 =fREF ÷ 2 0-125 MHz n/a 1 0 1 Test mode: PLL bypass fQ0-9 =fREF ÷ 4 0-62.5 MHz n/a 1 1 0 PLL mode (high frequency range) fQ0-9 =fREF 100 to 250 MHz fVCO =fREF 2 1 1 1 PLL mode (low frequency range) fQ0-9 =fREF 50 to 125 MHz fVCO =fREF 4 Power Supply Filtering The ASM5I9658 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The ASM5I9658 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the ASM5I9658. Figure 3. illustrates a typical power supply filter scheme. The ASM5I9658 frequency and phase stability is most susceptible to noise with spectral content in the 100KHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 12 mA (20 mA maximum), assuming that a minimum of 2.835V must be maintained on the VCC_PLL pin. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide attenuation greater than 40 dB for noise whose spectral content is above 100 KHz. In the example RC filter shown in Figure 3.“VCC_PLL Power Supply Filter”, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the ASM5I9658 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power |
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